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? semiconductor components industries, llc, 2000 august, 2000 rev. 4 1 publication order number: mc14521b/d mc14521b 24-stage frequency divider the mc14521b consists of a chain of 24 flipflops with an input circuit that allows three modes of operation. the input will function as a crystal oscillator, an rc oscillator, or as an input buffer for an external oscillator. each flipflop divides the frequency of the previous flipflop by two, consequently this part will count up to 2 24 = 16,777,216. the count advances on the negative going edge of the clock. the outputs of the last sevenstages are available for added flexibility. ? all stages are resettable ? reset disables the rc oscillator for low standby power drain ? rc and crystal oscillator outputs are capable of driving external loads ? test mode to reduce test time ? v dd and v ss pins brought out on crystal oscillator inverter to allow the connection of external resistors for lowpower operation ? supply voltage range = 3.0 vdc to 18 vdc ? capable of driving two lowpower ttl loads or one lowpower schottky ttl load over the rated temperature range. maximum ratings (voltages referenced to v ss ) (note 2.) symbol parameter value unit v dd dc supply voltage range 0.5 to +18.0 v v in , v out input or output voltage range (dc or transient) 0.5 to v dd + 0.5 v i in , i out input or output current (dc or transient) per pin 10 ma p d power dissipation, per package (note 3.) 500 mw t a ambient temperature range 55 to +125 c t stg storage temperature range 65 to +150 c t l lead temperature (8second soldering) 260 c 2. maximum ratings are those values beyond which damage to the device may occur. 3. temperature derating: plastic ap and d/dwo packages: 7.0 mw/ c from 65 c to 125 c this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. for proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). unused outputs must be left open. http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information mc14521bcp pdip16 2000/box mc14521bd soic16 48/rail mc14521bdr2 soic16 2500/tape & reel 1. for ordering information on the eiaj version of the soic packages, please contact your local on semiconductor representative. marking diagrams 1 16 pdip16 p suffix case 648 mc14521bcp awlyyww soic16 d suffix case 751b 1 16 14521b awlyww soeiaj16 f suffix case 966 1 16 mc14521b alyw mc14521bfel soeiaj16 see note 1. mc14521bfr2 soeiaj16 see note 1. mc14521bf soeiaj16 see note 1.
mc14521b http://onsemi.com 2 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 q20 q21 q22 v dd in 1 q18 q19 out 2 v ss reset q24 v ss in 2 v dd q23 block diagram output count capacity q18 2 18 = 262,144 q19 2 19 = 524,288 q20 2 20 = 1,048,576 q21 2 21 = 2,097,152 q22 2 22 = 4,194,304 q23 2 23 = 8,388,608 q24 2 24 = 16,777,216 stages 18 thru 24 stages 1 thru 17 q18 q19 q20 q21 q22 q23 q24 10 11 12 13 14 15 1 2 6 in 2 9 in 1 7 reset v dd = pin 16 v ss = pin 8 5 3 4 out 1 v dd v ss out2
mc14521b http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) v dd 55 c 25 c 125 c characteristic symbol v dd vdc min max min typ (4.) max min max unit output voltage a0o level v in = v dd or 0 v ol 5.0 10 15 e e e 0.05 0.05 0.05 e e e 0 0 0 0.05 0.05 0.05 e e e 0.05 0.05 0.05 vdc a1o level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 e e e 4.95 9.95 14.95 5.0 10 15 e e e 4.95 9.95 14.95 e e e vdc input voltage a0o level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 e e e 1.5 3.0 4.0 e e e 2.25 4.50 6.75 1.5 3.0 4.0 e e e 1.5 3.0 4.0 vdc a1o level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 e e e 3.5 7.0 11 2.75 5.50 8.25 e e e 3.5 7.0 11 e e e vdc output drive current (v oh = 2.5 vdc) source (v oh = 4.6 vdc) pins 4 & 7 (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 5.0 10 15 1.2 0.25 0.62 1.8 e e e e 1.0 0.2 0.5 1.5 1.7 0.36 0.9 3.5 e e e e 0.7 0.14 0.35 1.1 e e e e madc (v oh = 2.5 vdc) source (v oh = 4.6 vdc) pins 1, 10, (v oh = 9.5 vdc) 11, 12, 13, 14 (v oh = 13.5 vdc) and 15 5.0 5.0 10 15 3.0 0.64 1.6 4.2 e e e e 2.4 0.51 1.3 3.4 4.2 0.88 2.25 8.8 e e e e 1.7 0.36 0.9 2.4 e e e e madc o (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 0.64 1.6 4.2 e e e 0.51 1.3 3.4 0.88 2.25 8.8 e e e 0.36 0.9 2.4 e e e madc input current i in 15 e 0.1 e 0.00001 0.1 e 1.0 m adc input capacitance (v in = 0) c in e e e e 5.0 7.5 e e pf quiescent current (per package) i dd 5.0 10 15 e e e 5.0 10 20 e e e 0.005 0.010 0.015 5.0 10 20 e e e 150 300 600 m adc total supply current (5.) (6.) (dynamic plus quiescent, per package) (c l = 50 pf on all outputs, all buffers switching) i t 5.0 10 15 i t = (0.42 m a/khz) f + i dd i t = (0.85 m a/khz) f + i dd i t = (1.40 m a/khz) f + i dd m adc 4. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. 5. the formulas given are for the typical characteristics only at 25 c. 6. to calculate total supply current at loads other than 50 pf: i t (c l ) = i t (50 pf) + (c l 50) vfk where: i t is in m a (per package), c l in pf, v = (v dd v ss ) in volts, f in khz is input frequency, and k = 0.003.
mc14521b http://onsemi.com 4 ????????????????????????????????? ????????????????????????????????? switching characteristics (7.) (c l = 50 pf, t a = 25 c) characteristic symbol v dd vdc min typ (8.) max unit output rise and fall time (counter outputs) t tlh , t thl = (1.5 ns/pf) c l + 25 ns t tlh , t thl = (0.75 ns/pf) c l + 12.5 ns t tlh , t thl = (0.55 ns/pf) c l + 12.5 ns t tlh , t thl 5.0 10 15 e e e 100 50 40 200 100 80 ns propagation delay time clock to q18 t phl , t plh = (1.7 ns/pf) c l + 4415 ns t phl , t plh = (0.66 ns/pf) c l + 1667 ns t phl , t plh = (0.5 ns/pf) c l + 1275 ns t phl , t plh 5.0 10 15 e e e 4.5 1.7 1.3 9.0 3.5 2.7 m s clock to q24 t phl , t plh = (1.7 ns/pf) c l + 5915 ns t phl , t plh = (0.66 ns/pf) c l + 2167 ns t phl , t plh = (0.5 ns/pf) c l + 1675 ns 5.0 10 15 e e e 6.0 2.2 1.7 12 4.5 3.5 propagation delay time reset to q n t phl = (1.7 ns/pf) c l + 1215 ns t phl = (0.66 ns/pf) c l + 467 ns t phl = (0.5 ns/pf) c l + 350 ns t phl 5.0 10 15 e e e 1300 500 375 2600 1000 750 ns clock pulse width t wh(cl) 5.0 10 15 385 150 120 140 55 40 e e e ns clock pulse frequency f cl 5.0 10 15 e e e 3.5 9.0 12 2.0 5.0 6.5 mhz clock rise and fall time t tlh , t thl 5.0 10 15 e e e e e e 15 5.0 4.0 m s reset pulse width t wh(r) 5.0 10 15 1400 600 450 700 300 225 e e e ns reset removal time t rem 5.0 10 15 30 0 40 200 160 110 e e e ns 7. the formulas given are for the typical characteristics only at 25 c. 8. data labelled atypo is not to be used for design purposes but is intended as an indication of the ic's potential performance. figure 1. power dissipation test circuit and waveform pulse generator v dd v dd v dd v ss v ss q18 q19 q20 q21 q22 q23 q24 c l c l c l c l c l c l c l i d in 2 r 500 m f 0.01 m f ceramic 20 ns 20 ns v dd 0 v v in 50% duty cycle 90% 10% 50%
mc14521b http://onsemi.com 5 figure 2. switching time test circuit and waveforms pulse generator q18 q19 q20 q21 q22 q23 q24 in 2 r v dd v dd v ss v ss c l c l c l c l c l c l c l v dd 20 ns 20 ns 20 ns 10% 50% 90% 10% 50% 90% in 2 q n t plh t phl t tlh t thl t wl t wh characteristic 500 khz circuit 50 khz circuit unit crystal characteristics resonant frequency equivalent resistance, r s 500 1.0 50 6.2 khz k w external resistor/capacitor values r o c t c s 47 82 20 750 82 20 k w pf pf frequency stability frequency change as a function of v dd (t a = 25 c) v dd change from 5.0 v to 10 v v dd change from 10 v to 15 v frequency change as a function of temperature (v dd = 10 v) t a change from 55 c to + 25 c mc14521 only complete oscillator* t a change from +25 c to+125 c mc14521 only complete oscillator* + 6.0 + 2.0 4.0 + 100 2.0 160 + 2.0 + 2.0 2.0 + 120 2.0 560 ppm ppm ppm ppm ppm ppm *complete oscillator includes crystal, capacitors, and resistors. ??????????????????? ? ????????????????? ? ??????????????????? figure 4. typical data for crystal oscillator circuit figure 3. crystal oscillator circuit v dd v dd v dd v ss v ss out 1 out 2 q18 q19 q20 q21 q22 q23 q24 in 1 in 2 r r* r* c s c t r o 18 m * optional for low power operation, 10 k w r 70 k w .
mc14521b http://onsemi.com 6 figure 5. rc oscillator stability figure 6. rc oscillator frequency as a function of r tc and c -55 -25 0 25 50 75 100 125 8.0 4.0 0 -4.0 -8.0 -12 -16 frequency deviation (%) t a , ambient temperature ( c), device only test circuit figure 7 v dd = 15 v 10 v 5.0 v r tc = 56 k w , c = 1000 pf r s = 0, f = 10.15 khz @ v dd = 10 v, t a = 25 c r s = 120 k w , f = 7.8 khz @ v dd = 10 v, t a = 25 c { f, oscillator frequency (khz) 100 50 20 10 5.0 1.0 2.0 0.1 0.2 0.5 1.0 k 10 k 100 k 1.0 m 0.0001 0.001 0.01 0.1 r tc , resistance (ohms) c, capacitance ( m f) v dd = 10 v f as a function of r tc (c = 1000 pf) (r s 2r tc ) test circuit figure 7 f as a function of c (r tc = 56 k w ) (r s = 120 k) figure 7. rc oscillator circuit figure 8. functional test circuit out 1 out 2 q18 q19 q20 q21 q22 q23 q24 in 1 in 2 r v dd v dd v ss v ss v dd r s r tc c q18 q19 q20 q21 q22 q23 q24 out 1 out 2 in 1 in 2 r v dd v dd v ss v ss pulse generator
mc14521b http://onsemi.com 7 ????????????????????????????????? ????????????????????????????????? functional test sequence inputs outputs comments reset in 2 out 2 v ss v dd q18 thru q24 counter is in three 8stage sections in parallel mode counter is reset. in 2 and 1 0 0 v dd gnd 0 counter is reset. in 2 and out 2 are connected together a test function (see figure 8) has been included for the reduction of test time re q uired to 0 1 1 first a0o to a1o transition on in 2, out 2 node. included for the reduction of test time required to exercise all 24 counter stages. this test function divides the counter into three 8stage sections, and 255 counts are loaded in each of the 8stage sections in parallel. all flipflops are now at a lo g ic a1o. the counter is now returned 0 1 e e e 0 1 e e e 255 a0o to a1o transitions are clocked into this in 2, out 2 node. now at a logic 1 . the counter is now returned to the normal 24stages in series configuration. one more pulse is entered into input 2 (in 2) 1 1 1 the 255th a0o to a1o transition. oeoeuseseeedou() which will cause the counter to ripple from an all a1o state to an all a0o state. 0 0 0 0 gd 1 1 1 0 gnd v dd 1 counter converted back to 24stages in series mode. 1 0 dd 1 out 2 converts back to an output. 0 1 0 counter ripples from an all a1o state to an all a0o stage.
mc14521b http://onsemi.com 8 logic diagram v dd 5 reset 2 9 in 1 6 in 2 7 out 1 3 v ss 4 out 2 stages 3 thru 7 stages 11 thru 15 12 8 910 16 17 18 19 20 21 22 23 24 10 q18 11 q19 12 q20 13 q21 14 q22 15 q23 1 q24 v dd = pin 16 v ss = pin 8
mc14521b http://onsemi.com 9 package dimensions pdip16 p suffix plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01
mc14521b http://onsemi.com 10 package dimensions soic16 d suffix plastic soic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc14521b http://onsemi.com 11 package dimensions h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z soeiaj16 f suffix plastic eiaj soic package case 96601 issue o
mc14521b http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402745 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc14521b/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk

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